1. Field of the Invention
This invention relates to a process for forming slots for isolating active regions in an integrated circuit and, more particularly, relates to a process for forming slots which have an immunity to inversion across the mouth of the slot after it is filled.
2. Discussion of Background and Prior Art
The use of slots, also known as trenches or grooves, is becoming more common in isolating individual devices within an integrated circuit. For certain applications, such slots or trenches will be replacing the traditional approaches of pn junction isolation and oxide isolation. See, e.g., D. N. K. Wang et al., "Reactive-Ion Etching Eases Restrictions on Materials and Feature Sizes", Electronics, Nov. 3, 1983, pp. 157, 159.
The traditional technique for fabricating slots, the so-called cut-and-fill technique, has generally not been widely implemented in the semiconductor industry because it has utilized chemical etches which etch the silicon along specified crystallographic planes. Except for special crystallographic orientations not readily obtainable in conventional device processing, the shape of the etched regions tends to be a V with a high ratio of lateral spacing to depth. This has not been particularly suitable for high level integration in integrated circuits. Also, while it has been possible with the above-mentioned special crystallographic orientations along with careful masking and etching to fabricate long, narrow grooves in silicon wafers, it has not been possible by chemical means alone to produce arbitrary shapes or small holes. The direction of etching follows the orientation of the crystal axes so that arbitrary shapes are not possible. See, e.g., D. L. Kendall, "Vertical Etching of Silicon At Very High Aspect Ratios", Annual Review of Materials Science, 1979, v. 9, pp. 373-403.
The increasing use of slots or trenches as discussed above is due principally to the availability of physical etching equipment such as reactive-ion etch equipment supplied by companies such as Anelva, ETS, Varian and others. Since the ion beams or plasma action is directed, anisotropic etching is inherent and therefore the etching of arbitrary shapes is possible. Reactive species such as SF.sub.6, CCl.sub.2 F.sub.2 or CCl.sub.4 are used in the beams so that the benefits and effects of both physical and chemical etching may be obtained. There has also been a growing use of selective etchants in semiconductor fabrication processes to produce structural features without having to use additional masking steps. See, e.g., H. W. Lehmann et al., "Dry Etching For Pattern Transfer", J. Vacuum Science and Technology, v. 17, No. 5, September/October 1980, pp. 1177; and L. M. Ephrath, "Reactive Ion Etching for VLSI", IEEE Transactions on Electron Devices, v. Ed-28, No. 11, November 1981, p. 1315. In practice these equipments and techniques are used to form slots which are then filled with a suitable filler material in order to produce structural integrity. Filling is accomplished either by flowing the material into the slot or by depositing a film within a slot by isotropic film processes. Finally, the slot-containing substrates are planarized and serve as isolation barriers between active regions in an integrated circuit. See, e.g., H. B. Pogge, "Process of Forming Recessed Dielectric Regions In A Monocrystalline Silicon Substrate", U.S. Pat. No. 4,307,180; A. Muramatsa, "Method of Manufacturing A Semiconductor Device Utilizing Etch and Refill To Form Isolation Regions", U.S. Pat. No. 4,369,565; or C. T. Horng et al., "Process for Fabricating A Self-Aligned Micrometer Bipolar Transistor Device", U.S. Pat. No. 4,333,227.
Since bipolar devices typically have a vertical structure and require isolation down to the interface of the epitaxial layer with the substrate, isolation slots may need to be as deep as 5-7 microns. For MOS devices, which have a horizontal orientation and operate on surface conduction principles, slots for isolating MOS devices may be much shallower. As a consequence, to isolate p-wells or n-wells in CMOS devices, the slot need only be on the order of 3 microns deep. To isolate against unwanted surface inversion between adjacent devices of the same type the slots need only be about 1 micron deep.
For CMOS devices generally, and particularly for highly integrated CMOS devices, it has been necessary to provide isolation to prevent latchup. The phenomenon is based upon the parasitic bipolar transistors which are formed inherently by the various physical regions which make up the CMOS devices. These transistors are superimposed upon the n-channel and p-channel devices present in the CMOS structure. Upon the occurrence of certain operating conditions they may latch up the device and impede the operation of the CMOS circuitry. See, e.g., B. L. Gregory et al., "Latchup in CMOS Integrated Circuits", IEEE Transactions on Nuclear Science, v. NS20, pp. 293-299 (1973). This phenomenon can be understood by reference to FIGS. 1, 1a and 1b. In FIG. 1 a typical CMOS structure is shown which has a p-channel device 10 formed in an n-type substrate 18 and an n-channel device 11 formed in a p-well 19. The parasitic devices can be seen by connecting a phantom terminal A to drain region 14 of the p-channel device 10 and a phantom terminal B to the source region 15 of the n-channel device 11. The parasitic SCR as shown in FIG. 1a or the two connected parasitic bipolar transistors as shown in FIG. 1b are inherently formed. When these devices latch up the CMOS circuit is rendered dysfunctional. To avoid latchup it has been proposed, as shown in FIG. 2, to incorporate n+ region 26 between p+ drain region 14 of p-channel device 10 and p-well 19 and also to incorporate p+ region 27 between n+ source region 15 of n-channel device 11 and n-substrate 18. Such a solution is not acceptable for high density CMOS circuits since too much additional area is dedicated to solving the latchup problem. Another approach is to employ circuit techniques which work against latchup such as using a charge pump to bias the substrate. See, e.g., Electronics, Feb. 23, 1984, p. 54. This approach adds undesired complexity and may require the use of proprietary circuit technology. Oxide isolation, of the type shown in FIG. 3, has been utilized for field isolation of CMOS integrated circuits. By definition, field oxide isolation means isolating devices by growing thick field oxide 30, 31, 32 between these devices. This has proven to be generally satisfactory for devices of medium scale integration. However, for large scale integration (LSI) and very large scale integration (VLSI), oxide isolation has occupied an undesirably large amount of the available surface area. It is therefore desirable to be able to provide an isolation technique which will prevent latchup and may be used to isolate wells from substrate regions but which does not require too much additional area or an appreciable amount of additional processing.
In principle, the use of narrow isolation slots will allow high level integration to be accomplished. With the availability of dry etching equipment, slots as narrow as one micron can be fabricated. However, as slots become progressively more narrow, especially for n-channel devices, the likelihood of spurious conduction or inversion occurring across the mouth of the slot becomes more likely due to the positive charge on the surface of the slot. To prevent such inversion, stopper regions have been proposed adjacent the edges of the mouth of the slot. Conventional slot formation techniques, however, tend to undercut the masking layers which define the slot and eat into these stopper regions, thereby making inversion more likely.
It is therefore an object of the present invention to provide a process for fabricating isolation slots for device isolation in integrated circuits which have an immunity to surface inversion.
It is another object of the present invention to provide a process for fabricating isolation slots which does not require inordinately high implantation dosages or a long drive-in in order to dope the stopper regions that serve to impede inversion across the mouths of the filled slots.
It is another object of the present invention to provide a process which prevents the undercutting of the semiconductor substrate underneath the mask adjacent the mouth of the slot.